1. Field of the Invention
The present invention relates to a dynamic random access memory device, and more particularly, to a dynamic random access memory device having reduced power consumption and a method of determining a refresh cycle thereof.
This application claims priority from Korean Patent Application No. 10-2005-0115006 filed on Nov. 29, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.
2. Discussion of Related Art
Dynamic random access memory devices include a plurality of memory cells, each of which has a transistor that serves as a switch and a capacitor that stores data. However, initial data stored in the capacitor may be lost due to leakage current generated in a PN junction of a MOS transistor. Accordingly, in dynamic random access memory devices, a refresh operation is required to recharge data in the memory cell before data is lost. The refresh operation includes an automatic refresh operation, a self refresh operation, and so on. In the self refresh operation, refresh is performed while the dynamic random access memory device sequentially changes an internal address in response to a refresh instruction signal.
The self refresh operation is repeated according to an internally defined cycle. The recharge cycle is referred to as a refresh cycle tREF. The refresh cycle is determined based on the data retention characteristics, which are not constant due to changes in process, voltage, and temperature (PVT). However, during this refresh operation, the dynamic random access memory device consumes high standby power as compared to a static RAM (SRAM) or flash memory device. Accordingly, there is a need for a refresh cycle associated with a dynamic random access memory device which requires reduced power consumption.